Designing Using BGA and Flip Chip Technology
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This book was written to furnish information about the evolution of packages and how to use them to design advance level products. The first section of this book serves as an introduction to the technologies available for designers. Section 2 presents important information about designing including information about boards and assembly. Section 3 is all about flex circuitry materials. Flex will play a major role in future solutions. Section 4 explains about land patterns. Section 5 is design for manufacturability. Section 6 is documentation for assembly and fabrication. Take your time and read through this publication. It is loaded with insight and should help you in your next generation designs. Table of Contents. |
Table of Contents
1 - Packaging Evolution
| 1.1 |
Package Pricing Trends |
| 1.2 |
Metric Conversion |
| 1.3 |
Package Trends |
| 1.4 |
COB Technology |
| 1.5 |
Wirebonding Technology |
| 1.5.1 |
Ball Bonding |
| 1.5.2 |
Wedge Bonding |
| 1.5.3 |
Thermosonic Bonding |
| 1.5.4 |
Thermocompression Bonding |
| 1.5.5 |
Ultrasonic Bonding |
| 1.6 |
Wirebonding Parameters |
| 1.7 |
Flip Chip Technology |
| 1.8 |
Multiple-chip Technology |
| 1.8.1 |
MCM - Flex |
| 1.9 |
TCP Technology |
| 1.10 |
BGA Technology |
| 1.10.1 |
PBGA |
| 1.10.2 |
BGA Standards |
| 1.10.3 |
BGA Lead Configurations |
| 1.10.4 |
BGA Row and Column Markings |
| 1.10.5 |
Sockets |
| 1.10.6 |
PBGA Lids |
| 1.10.7 |
BGA Thermals |
| 1.10.8 |
BGA Moisture Sensitivity |
| 1.10.9 |
Super BGA |
| 1.10.10 |
Small BAll BGA |
| 1.11 |
Ceramic BGA's |
| 1.12 |
Ceramic Column Grid Array |
| 1.13 |
Tape Ball Grid Array |
| 1.14 |
Chip Scale Packaging |
2 - PCB and Design
| 2.1 |
PC Board Design Decisions |
| 2.2 |
Thin Boards |
| 2.3 |
Vias |
| 2.4 |
Trace Widths |
| 2.5 |
Trace Spacing |
| 2.6 |
Routing Layers |
| 2.7 |
Layer Structures and Choices |
| 2.8 |
Thermal |
| 2.9 |
Solder Mask |
| 2.10 |
Plating Types |
| 2.11 |
Bare Board Test |
| 2.12 |
Placement Considerations |
| 2.12.1 |
COB Placment |
| 2.12.2 |
Flip Chip Clearance Considerations |
| 2.12.3 |
BGA Packages Placement Considerations |
| 2.13 |
Advance Packaging Decisions |
| 2.14 |
High-Density Assembly |
| 2.15 |
Double-Side Mount Assemblies |
| 2.16 |
Wave Soldering Limitations for New Technologies |
| 2.17 |
Conserving Real Estate |
3 - Flex Circuitry
| 3.1 |
Flex Terms and Considerations |
| 3.2 |
Evolving Flex |
| 3.3 |
Cost of Flex |
| 3.4 |
Epoxy Glass Core |
| 3.5 |
Cover Coat |
| 3.6 |
Copper Conductors |
| 3.7 |
Sculptured Conductors |
| 3.8 |
Polymer Conductors |
| 3.9 |
Flip Chip on Flex |
| 3.10 |
Types of Flex Designs for Assembly |
| 3.11 |
Assembly Requirements for Flex |
| 3.12 |
Connections to Flex |
| 3.13 |
Multilayer Flex |
4 - Land Patterns
| 4.1 |
Land Patterns for BGA Packages |
| 4.2 |
Solder Mask Defined Pads |
| 4.3 |
Non-Solder Mask Defined Pads |
| 4.4 |
BGA Land Options |
| 4.5 |
Staggered Ball Patterns |
| 4.6 |
BGA Collapsible Ball Lead |
| 4.7 |
Non-Collapsible BGA Ball Lands |
| 4.8 |
Lands for Columns Used on BGA Packages |
| 4.9 |
Vias in Lands for BGA Leads |
| 4.10 |
BGA Land Pattern Vs Reliability |
| 4.11 |
BGA Layer Count |
| 4.12 |
BGA Routing Channels |
| 4.13 |
Peripheral BGA Designs |
| 4.14 |
BGA Pinouts |
| 4.14.1 |
BGA Power and Ground |
| 4.14.2 |
Decoupling Capacitors |
| 4.14.3 |
Terminator Location for Peripheral PBGA |
| 4.15 |
BGA Pads to Vias |
| 4.16 |
Enhancing BGA for X-Ray Inspection |
| 4.17 |
Flip Chip and COB Lands |
| 4.17.1 |
Flip Chip Land Patterns |
| 4.17.2 |
COB Land Patterns |
5 - Manufacturing Issues
| 5.1 |
High-Density Assembly |
| 5.1.1 |
Fiducials |
| 5.1.2 |
Alignment Marks for BGA's |
| 5.1.3 |
Special Centering Pads for BGA's |
| 5.1.4 |
COB Design for Assembly Considerations |
| 5.1.5 |
Flip Chip Design for Assembly Considerations |
| 5.2 |
Panels and Pallets |
| 5.3 |
PCB Plating |
| 5.4 |
Inspection and Repair Issues |
| 5.4.1 |
BGA Packages |
| 5.4.2 |
Flip Chip Technology |
| 5.4.3 |
COB |
| 5.5 |
Cleaning Issues |
| 5.6 |
In-Circuit Test Issues |
6 - Fabrication and Documentation
| 6.1 |
Assembly Documentation |
| 6.2 |
Flex Fabrications |
| 6.2.1 |
Creating Vias |
| 6.2.2 |
Cutting Edges |
| 6.2.3 |
Cover Layer |
| 6.2.4 |
Stack Up |
| 6.2.5 |
Stress Points |
| 6.3 |
PC Fabrication |
| 6.3.1 |
PCB Plating Considerations |
| 6.3.2 |
Immersion Process |
| 6.3.3 |
Electroplating Process |
| 6.3.4 |
Electroless Process |
| 6.4 |
Selecting the Plating Composition |
| 6.5 |
Organic Coatings |
| 6.6 |
Fabrication Notes |
Author: James C. Blankenhorn
Printed: July 2001
ISBN: 1-882812-15-8
Pages: full color 127 pages 8.5" x 11" |
Author: James C. Blankenhorn
James C. Blankenhorn is President and founder (1985) of SMT Plus Inc., located in Scotts Valley, California. His experience in SMT began as Vice President of Design and Prototyping for AWI, the first SMT subcontract design and assembly firm for SMT from 1983-1985. His work established many of the design guidelines and processes used in the SMT industry today. Mr. Blankenhorn sold the design and assembly operations to and was General Manager and Vice President of Design for Jabil Circuit from 1988-1991, setting up multiple design centers and managing prototype assembly. Mr. Blankenhorn returned to SMT Plus to direct its activities. Having identified the growing needs of industry for education, SMT Plus has emerged since 1996 as a leader in the production of advanced multimedia technical training products and development tools for the SMT and telecommunications industries. Prior to his involvement with SMT, Mr. Blankenhorn was a MOS designer for Motorola and TI and product line manager for memory and microprocessors for Honeywell for 8 years. For 3 years thereafter he was involved in startups in IC packaging, test and burn-in as General Manager for Test International and Vice President of Sales for IC Link.
Mr. Blankenhorn is an active member of the SMTA, a co-founder of the SMTA in 1984, recipient of the 1996 Founders Award for Distinguished Service, and served twice as technical chairman for the Silicon Valley SMTA chapter. He is a speaker at conferences worldwide and has authored over twenty books on SMT design, packaging, and processing. He holds a BSEE degree from Arizona State University and is listed in Who's Who in America.
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