Extremely Dense Designs and DFM
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This book is a must read publication for design, manufacturing, and product engineers. If you have a need to design next-generation products using smaller packages, it needs to be as dense as possible, and it may or may not have RF circuitry on it, and you are not sure if your design rules and process are going to work then this book is for you. The design of new modern products using smaller and smaller components creates problems for both design and manufacturing. From a designer's perspective the performance of the product is one issue. Another issue is how close can components be placed and sustained in manufacturing. Another is to know the land patterns are not going to cause problems. And yet another is to know the board size, possible panels or pallets will work, and what are the real issues and limits. Table of Contents. |
This new publication investigates these issues by starting with component tolerances down to 0201's, Micro SMD, CSP, SOIC's, QFP's and etc. Then it looks at studies performed on process and assembly limits, combines it with research on current high volume products to learn things very few in the industry know such as the limits of combining new small packages with SMT, development of very-high density design guidelines never published anywhere that drive spacings to as close as .006", and identifies where and how process limitations occur and the possible solutions to overcome these obstacles.
For manufacturing it is vital to know where the limits and problems areas are going to come from when you attempt to implement designs using small packages and or mixing new small footprints for packages with traditional SMT. There are very serious problems quantified in this book with solutions and ideas on how you can avoid those significant yield losses that those not in the know are having happen to them.
The book contains eight chapters and is filled with color photos and charts:
- Component Package Specs and Tolerances
- High Speed Design Considerations
- Printed Circuit Boards
- Density Studies and Research
- Land Patterns
- Placement Rules for Very Dense Designs
- Dense Assembly Requirements
- Implementation
Table of Contents
Section 1 Component Package Specs and Tolerances
1.1 Introduction
1.1.1 Cell phones
1.1.2 PDA's
1.1.3 Sub-Notebook Computers
1.1.4 Disk Drives
1.2 Industry Package Standards
1.3 Metric vs Inch Dimensions
1.4 Dimensioning and Tolerancing
1.4.1 Root Mean Square Method
1.4.2 Nominal Value
1.4.3 Minimum Value
1.4.4 Maximum Value
1.5 Plating Types
1.5.1 Gold Plating
1.5.2 Solder Plating
1.5.3 Solder Dip
1.6 IPC-A-610 Specifications
1.7 Passive Component Specifications
1.7.1 0805 Chip Component
1.7.2 0603 Chip Component
1.7.3 Mechanical Variances for 0603 Capacitors
1.7.4 0402 Chip Component
1.7.5 Mechanical Variances for 0402 Capacitors
1.7.6 0201 Resistors and Capacitors
1.7.7 Inward Leads
1.7.8 Ceramic Resistor Networks
1.8 Gullwing Leads
1.8.1 Wide Gullwing
1.8.2 Narrow Gullwing Leads
1.9 J Leads
1.10 Solder Bumps on WL-CSP
1.11 Solder Bumps on CSP
1.12 Solder Bumps on BGA's
1.13 Small Signal Transistors
1.14 RF Transistors
1.14.1 Plastic Body
1.14.2 Ceramic Body
1.15 Predeposited Solder on Leads
Section 2 High Speed Design Considerations
2.1 High Speed vs Density
2.1.1 Semiconductor Technology
2.2 Parastics
2.3 Coupling
2.3.1 Electromagnetic and Electrostatic Fields
2.3.2 Impedance versus Spacing
2.3.3 Coupling Model
2.3.4 Critical Length
2.4 Reflections
2.4.1 Source of Reflections
2.4.2 Stubs
Section 3 Printed Circuit Boards
3.1 Board Fabrication
3.2 Flexible Circuit Boards
3.3 Rigid-Flex Circuit Boards
3.3.1 Key Fabrication Tolerances
3.4 Trace Width
3.4.1 5 mil lines and above
3.4.2 3 mil lines
3.4.3 1 mil lines
3.5 Trace Spacing
3.5.1 Considerations
3.5.2 Rules for spacing
3.6 Small Holes
3.6.1 Board thickness factors
3.6.2 Difficulty in small holes
3.6.3 Internal clearances
3.6.4 Microvias and HDI Technology
3.6.5 Microvia Process
3.6.6 Cost considerations
3.7 Power Planes
3.7.1 Layer Stackup
3.7.2 Ground Planes
3.7.3 Stackup Options
3.7.4 Power to Ground Decoupling
3.7.5 Bulk Decoupling
3.7.6 EMI Containment
3.8 Solder Mask
3.8.1 Liquid Photo-imaged
3.8.2 Tolerances
3.9 Silkscreen
3.9.1 Photo Imaged epoxy
3.9.2 Silkscreen Tolerances
3.10 Panelization
3.10.1 Panelization Tolerance
3.10.2 Depanelization
3.11 Fiducials
3.11.1 Purpose of Fiducials
3.11.2 Global Fiducials
3.11.3 Local Fiducials
Section 4 Density Studies and Research
4.1 Studies of High-Density
4.1.1 Land Pattern Design
4.1.2 Solder Paste
4.1.3 Stencils
4.1.4 Print
4.1.5 Component Placement
4.1.6 Reflow Profiles
4.2 Failure Types in Experiments
4.3 Test Boards
4.3.1 Paste and Reflow Experiment
4.3.2 Assembly vs Pattern Experiments
4.3.3 Lead Free Assembly Experiments
4.3.4 Pad to Pad Spacing Experiment
4.3.5 Conclusions from Experiments
4.4 Production Product Analysis
4.4.1 Production Product Conclusions
Section 5 Land Patterns
5.1 Land Pattern Creation Rules
5.2 Solder Joint Strength
5.3 Current Land Patterns
5.3.1 IPC Patterns
5.3.2 SMT Plus Chip Component Land Patterns
5.4 Solder Balls and Stencil Aperture Techniques
5.4.1 Solder Balls
5.5 High-Density Land Pattern Shape Modifications
5.6 Very High-Density Chip Component Land Patterns
5.6.1 Minimal Fillet Lands
5.6.2 Filletless Lands
5.6.3 Minimal Fillet Lands for Chip Components
5.7 Gullwing Land Patterns
5.7.1 SOT's
5.7.2 SOIC and QFP
5.8 BGA's
5.8.1 PBGA
5.8.2 Undersized Ball Patterns
5.8.3 CBGA
5.9 CSPs
5.9.1 0.8 mm patterns
5.9.2 0.5 mm patterns
5.10 Flip Chip Technology
5.11 Inward Gullwing Packages
5.11.1 Tab and Lug Lead Packages
5.12 Ceramic Leadless Packages
5.13 Plastic Leadless
5.13.1 Minimal Fillet Lands for Leadless Plastic Packages
5.14 Land Connections
Section 6 Placement Rules for Dense Designs
6.1 How close is close
6.2 Assuring Rules by Designing Test Structures
6.3 Equipment Capabilities
6.3.1 Placement Heads
6.3.2 Placement Pressure
6.4 Placement Rules for Passive to Passive Components
6.4.1 Orientation
6.4.2 Side by Side Placement
6.4.3 End to End Chip Component Placement
6.4.4 SOT to Chip Components
6.5 Placement Rules for Passive to Gullwing
6.6 Placement rules for Large Passives
6.7 Test Points
Section 7 Dense Assembly Requirements
7.1 Basis for Setting up a Model
7.1.1 Board Registration
7.1.2 Printed Circuit Boards
7.1.3 Solder Paste
7.1.4 Printing
7.1.5 Placement
7.1.6 Reflow
7.2 Factors Affecting Very Dense Design Rules
7.2.1 Components
7.2.2 Printed Circuit Boards
7.2.3 Assembly Equipment
7.3 Maintenance and Calibration
Section Implementation
8.1 Areas to Watch Out For
8.2 Steps for Implementation
8.3 Product Analysis
8.4 Test Vehicle Design
8.5 Process Analysis and Specification
8.6 Product Design
8.7 Process and Reliability Review
Price: $199.95
Author: James C. Blankenhorn
Edition: October 2001
ISBN: 1-882812-39-5
Pages: full color 126 pages |
Author: James C. Blankenhorn
James C. Blankenhorn is President and founder (1985) of SMT Plus Inc., located in Scotts Valley, California. His experience in SMT began as Vice President of Design and Prototyping for AWI, the first SMT subcontract design and assembly firm for SMT from 1983-1985. His work established many of the design guidelines and processes used in the SMT industry today. Mr. Blankenhorn sold the design and assembly operations to and was General Manager and Vice President of Design for Jabil Circuit from 1988-1991, setting up multiple design centers and managing prototype assembly. Mr. Blankenhorn returned to SMT Plus to direct its activities. Having identified the growing needs of industry for education, SMT Plus has emerged since 1996 as a leader in the production of advanced multimedia technical training products and development tools for the SMT and telecommunications industries. Prior to his involvement with SMT, Mr. Blankenhorn was a MOS designer for Motorola and TI and product line manager for memory and microprocessors for Honeywell for 8 years. For 3 years thereafter he was involved in startups in IC packaging, test and burn-in as General Manager for Test International and Vice President of Sales for IC Link.
Mr. Blankenhorn is an active member of the SMTA, a co-founder of the SMTA in 1984, recipient of the 1996 Founders Award for Distinguished Service, and served twice as technical chairman for the Silicon Valley SMTA chapter. He is a speaker at conferences worldwide and has authored over twenty books on SMT design, packaging, and processing. He holds a BSEE degree from Arizona State University and is listed in Who's Who in America.
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